1. Technical Field
Various embodiments generally relate to semiconductor devices, and more particularly, to semiconductor devices employing a data inversion scheme.
2. Related Art
Recently, a multi-bit pre-fetch scheme has been widely used in semiconductor devices. The semiconductor devices using the multi-bit pre-fetch scheme may generate multi-bit data from memory cells in parallel in response to a single command and may output the multi-bit data in synchronization with a clock signal through a single data input/output (I/O) pin or a plurality of I/O pins. If the multi-bit pre-fetch scheme is used in the semiconductor device, a column path of internal cores of the semiconductor device may be driven at a low frequency. The low frequency is equal to or less than half that of an external clock signal. Thus, the internal cores and the column path of the semiconductor device may be readily designed if the semiconductor device employs the multi-bit pre-fetch scheme.
Meanwhile, as a frequency of the external clock signal increases and the number of data pads through which data are outputted increases, the semiconductor device may be designed to have a wide I/O structure including thirty two or more data pads through which data are simultaneously outputted. If the data are simultaneously outputted through thirty two or more data pads of the semiconductor device, a lot of noise referred to as ‘simultaneous switching noise (SSN)’ may be generated in the output data and the semiconductor device may suffer from the SSN. The SSN may distort waveforms of the output data to degrade a signal integrity of the semiconductor device. In such a case, it may be difficult to obtain a high performance semiconductor device having an excellent I/O characteristic that high frequency systems require.